(1) Field of the Invention
This invention relates to a power semiconductor device and a fabrication method thereof, and more particularly relates to a trenched power semiconductor device and a fabrication method thereof.
(2) Description of the Prior Art
Planar power semiconductor device, such as a planar metal oxide semiconductor field effect transistor (MOSFET), which features a planar gate electrode on the substrate for controlling the gate channel parallel to the substrate, usually wastes a significant area for locating the planar gate electrode and thus restricts the reduction of cell pitch. In contrast, because the gate electrode of trenched power semiconductor device is embedded in the trench and the gate channel is shifted to vertical direction, cell pitch of the power semiconductor device can be further reduced to enhance integration.
FIG. 1 is a cross-section schematic view of a typical trenched MOSFET. As shown, the trenched MOSFET has an N-type heavily doped substrate 10, an N-type lightly doped epitaxial layer 12, a plurality of gate trenches 14, a plurality of gate structures 16, a plurality of P-type wells 17, a plurality of source regions 18, and an interlayer dielectric layer 19. Wherein, the N-type lightly doped epitaxial layer 12 is located on the N-type heavily doped substrate 10, the gate trenches 14 are formed in the N-type lightly doped epitaxial layer 12, and the gate structures 16 are located in the gate trenches 14. The P-type wells 17 surrounding the gate trenches 14 are formed in the upper portion of the N-type lightly doped epitaxial layer 12. A gate dielectric layer 15 encircling the gate structure 16 is utilized for separating the gate structures 16 and the P-type wells 17 as well as the N-type lightly doped epitaxial layer 12. The source region 18 is located in a surface layer of the P-type well 17 and surrounds the gate trenches 14. The interlayer dielectric layer 19 is located on the gate structure 16 and has a plurality of source contact windows formed therein to expose the source regions 18.
Generally, a source voltage of the trenched MOSFET is applied to the source regions 18 through a source metal layer (not shown) over the interlayer dielectric layer 19, a gate voltage is applied to the gate structures 16 through a gate metal layer (not shown) over the interlayer dielectric layer 19, and a drain voltage is applied to the N-type heavily doped substrate 10 through a drain metal layer (not shown) on the backside surface of the N-type heavily doped substrate 10. The electrodes on the opposite surfaces of the substrate restrict the usage of packaging technologies.
As mentioned above, the structure as well as the fabrication method of the trenched MOSFET is quite complicated. Thus, it is an important issue in the art to simplify the fabrication method of the trenched power semiconductor device in present